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january 2007 1 1/22 1 M36W0R6050T1 m36w0r6050b1 64 mbit (4 mb 16, multip le bank, burst) flash memory and 32 mbit (2 mb 16) psram, multi-chip package features multi-chip package ? 1 die of 64 mbit (4 mb 16) flash memory ? 1 die of 32 mbit (2 mb 16) pseudo sram supply voltage ?v ddf = v ddp = v ddqf = 1.7 v to 1.95 v low power consumption electronic signature ? manufacturer code: 20h ? device code (top flash configuration), M36W0R6050T1: 8810h ? device code (bottom flash configuration), m36w0r6050b1: 8811h package ?ecopack? flash memory programming time ? 8 s by word typical for fast factory program ? double/quadruple word program option ? enhanced factory program options memory blocks ? multiple bank memory array: 4 mbit banks ? parameter blocks (top or bottom location) synchronous / asynchronous read ? synchronous burst read mode: 66 mhz ? asynchronous/ synchronous page read mode ? random access: 70 ns dual operations ? program erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked ?wp f for block lock-down security ? 128-bit user programmable otp cells ? 64-bit unique device number common flash interface (cfi) 100 000 program/erase cycles per block psram access time: 70 ns asynchronous page read ? page size: 8 words ? first access within page: 70 ns ? subsequent read within page: 20 ns three power-down modes ? deep power-down ? partial array refresh of 4 mbits ? partial array refresh of 8 mbits fbga stacked tfbga88 (za) www.st.com
contents M36W0R6050T1, m36w0r6050b1 2/22 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 flash chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 flash output enable (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 flash write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 flash write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 flash reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 flash latch enable (l f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 flash clock (k f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 flash wait (wait f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 psram chip enable (e1 p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 psram chip enable (e2 p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.17 v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.18 v ddp supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.19 v ddqf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.20 v ppf program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M36W0R6050T1, m36w0r6050b1 contents 3/22 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of tables M36W0R6050T1, m36w0r6050b1 4/22 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. stacked tfbga88 8 10 mm - 8 10 ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M36W0R6050T1, m36w0r6050b1 list of figures 5/22 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch, package outline. . 18
description M36W0R6050T1, m36w0r6050b1 6/22 1 description the M36W0R6050T1 and m36w0r6050b1 combine two memories in a multi-chip package: a 64-mbit, multiple bank flash memory, the m58wr064ht/b, and a 32-mbit pseudo sram, the m69kb048bd. the purpose of this document is to describe how the two memory components operate with respect to each other. it must be read in conjunction with the m58wr064ht/b and m69kb048bd datasheets, where all specifications required to operate the flash memory and psram components are fully detailed. these datasheets are available from the st web site: www.st.com . recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga88 (8 10 mm, 8 10 ball array, 0.8 mm pitch) package. it is supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai12035 22 a0-a21 dq0-dq15 M36W0R6050T1 m36w0r6050b1 g f 16 w f rp f wp f e1 p g p w p ub p lb p v ss v ddf v ppf v ddp wait f l f k f v ddqf e f e2 p
M36W0R6050T1, m36w0r6050b1 description 7/22 table 1. signal names a0-a21 (1) 1. a21 is an address input for the flash memory component only. address inputs dq0-dq15 common data inputs/outputs v ddf flash memory power supply v ddqf flash memory power supply for i/o buffers v ppf common flash optional supply voltage for fast program & erase v ss ground v ddp psram power supply nc not connected internally du do not use as internally connected flash memory control functions l f latch enable input e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input k f burst clock wait f wait data in burst mode psram control functions e1 p chip enable input g p output enable input w p write enable input e2 p power-down input ub p upper byte enable input lb p lower byte enable input
description M36W0R6050T1, m36w0r6050b1 8/22 figure 2. tfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k f a4 a11 d e f du du w f v ss a19 a18 nc a5 a12 v ss nc lb p a9 a3 a13 v ppf nc a17 a10 a20 a2 a15 l f wp f nc a7 a14 a8 a1 a16 rp f ub p a6 wait f dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 g p dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g f v ddqf e f e2 p v ddp v ss v ss v ss v ss v ss v ddf v ddqf v ss du du du du du du a g h j k ai12037 l m v ddf nc w p e p nc nc nc nc nc nc nc nc v ddqf
M36W0R6050T1, m36w0r6050b1 signal descriptions 9/22 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a21) addresses a0-a21 are common inputs for the flash memory and psram components, whereas a21 is an address input for the flash memory component only. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the flash memory program/erase controller, and they select the cells to access in the psram. 2.2 data inputs/outputs (dq0-dq15) for the flash memory, the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. for the psram, the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub p ) is driven low. likewise, the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb p ) is driven low. 2.3 flash chip enable (e f ) the chip enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. when chip enable is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 flash output enable (g f ) the output enable pins control data outputs during flash memory bus read operations. 2.5 flash write enable (w f ) the write enable controls the bus write operation of the flash memories? command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first.
signal descriptions M36W0R6050T1, m36w0r6050b1 10/22 2.6 flash write protect (wp f ) write protect is an input that gives an additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to lock status table in m58wr064ht/b datasheet). 2.7 flash reset (rp f ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to the m58wr064ht/b datasheet, for the value of i dd2 . after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to the m58wr064ht/b datasheet). 2.8 flash latch enable (l f ) latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is low, v il , and it is inhibited when latch enable is high, v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. 2.9 flash clock (k f ) the clock input synchronizes the flash memory to the microcontroller during synchronous read operations; the address is latched on a cl ock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. 2.10 flash wait (wait f ) wait is a flash output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when flash chip enable is at v ih or flash reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the wait f signal is not gated by output enable. 2.11 psram chip enable (e1 p ) when asserted (low), the chip enable, e1 p , activates the memory state machine, address buffers and decoders, allowing read and write operations to be performed. when de- asserted (high), all other pins are ignored, and the device is automatically put in standby mode.
M36W0R6050T1, m36w0r6050b1 signal descriptions 11/22 2.12 psram chip enable (e2 p ) when de-asserted (low), the chip enable input e2 p , puts the device in power-down mode. this is the lowest power mode according to the configuration register settings (see m69kb048bd datasheet). 2.13 psram output enable (g p ) the output enable, g p , provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. 2.14 psram write enable (w p ) the write enable, w p , controls the bus write operation of the memory?s command interface. 2.15 psram upper byte enable (ub p ) the upper byte enable, ub p , gates the data on the upper byte data inputs/outputs (dq8- dq15) to or from the upper part of the selected address during a write or read operation. 2.16 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte data inputs/outputs (dq0- dq7) to or from the lower part of the selected address during a write or read operation. 2.17 v ddf supply voltage v ddf provides the power supply to the internal core of the flash memory component. it is the main power supplies for all flash memory operations (read, program and erase). 2.18 v ddp supply voltage the v ddp supply voltage supplies the power for all operations (read or write) and for driving the refresh logic, even when the device is not being accessed. 2.19 v ddqf supply voltage v ddqf provides the power supply for the flash memory i/o pins. this allows all outputs to be powered independently of the flash memory core power supply, v ddf .
signal descriptions M36W0R6050T1, m36w0r6050b1 12/22 2.20 v ppf program supply voltage v ppf is both a flash memory control input and a flash memory power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddqf ) v ppf is seen as a control input. in this case a voltage lower than v pplkf gives an absolute protection against program or erase, while v ppf > v pp1f enables these functions (see the m58wr064ht/b datasheet for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pphf it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. 2.21 v ss ground v ss is the common ground reference for all voltage measurements in the flash memory (core and i/o buffers) and psram components. note: each flash memory device in a sys tem should have its supply voltages (v ddf , v ddqf ) and the program supply voltage v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capaci tors should be as close as possible to the package). see figure 5: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents.
M36W0R6050T1, m36w0r6050b1 functional description 13/22 3 functional description the flash memory and psram components have separate power supplies but share the same grounds. they are distinguished by three chip enable inputs: e f for the flash memory and e1 p and e2 p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneous read operations on the flash memory and the psram which would result in a data bus contention. therefore it is recommended to put the other devices in the high impedance state when reading the selected device. figure 3. functional block diagram ai12.36 e1 p e2 p g p w p dq0-dq15 v ddf a0-a20 a21 32 mbit psram g f ub p lb p wait f 64 mbit flash memory v ddp e f k f w f l f rp f wp f v ppf v ddqf v ss
functional description M36W0R6050T1, m36w0r6050b1 14/22 1. x = don't care. 2. l f can be tied to v ih if the valid address has been previously latched. 3. depends on g f . 4. wait signal polarity is configured us ing the set configuration register comm and. refer to m58wr064ht/b datasheet for details. table 2. main operating modes operation e f g p w p l f rp f wait f (4) e1 p e2 p g p w p ub p lb p dq15-dq0 flash read v il v il v ih v il(2) v ih psram must be disabled flash data out flash write v il v ih v il v il(2) v ih flash data in flash address latch v il xv ih v il v ih flash data out or hi-z (3) flash output disable v il v ih v ih xv ih any psram mode is allowed flash hi-z flash standby v ih xx xv ih hi-z flash hi-z flash reset x x x x v il hi-z flash hi-z psram read flash memory must be disabled v il v ih v il v ih v il v il psram data out psram write v il v ih v ih v il v il v il psram data in output disable any flash mode is allowed. v il v ih v ih v ih x x psram hi-z psram standby v ih v ih x x x x psram hi-z psram deep power-down xv il x x x x psram hi-z
M36W0R6050T1, m36w0r6050b1 maximum rating 15/22 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?30 85 c t bias temperature under bias ?40 125 c t stg storage temperature ?55 125 c v io input or output voltage ?0.5 v ddqf +0.6 v v ddf flash memory core supply voltage ?0.2 2.45 v v ddqf input/output supply voltage ?0.2 2.45 v v ddp psram supply voltage ?0.5 3.6 v v ppf flash memory program voltage ?0.2 14 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
dc and ac parameters M36W0R6050T1, m36w0r6050b1 16/22 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter flash memory psram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v ddp supply voltage ? ? 1.7 1.95 v v ddqf supply voltage 1.7 1.95 ? ? v v ppf supply voltage (factory environment) 11.4 12.6 ? ? v v ppf supply voltage (application environment) ?0.4 v ddqf +0.4 ? ? v ambient operating temperature ?30 85 ?30 85 c load capacitance (c l )3050pf input rise and fall times 5 ns input pulse voltages 0 to v ddqf 0 to v ddp v input and output timing ref. voltages v ddqf /2 v ddp /2 v ai12057 v ddqf 0v v ddqf /2
M36W0R6050T1, m36w0r6050b1 dc and ac parameters 17/22 figure 5. ac measurement load circuit 1. sampled only, not 100% tested. please refer to the m58wr064ht/b and m69kb048bd datasheets for further dc and ac characteristics values and illustrations. table 5. device capacitance symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf ai12058 v ddqf c l c l includes jig capacitance 16.7k ? device under test 0.1f v ddqf 16.7k ? 0.1f v ddf
package mechanical M36W0R6050T1, m36w0r6050b1 18/22 6 package mechanical in order to meet environmental requirements, st offers the M36W0R6050T1 and m36w0r6050b1 devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 6. stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch, package outline 1. drawing is not to scale. a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
M36W0R6050T1, m36w0r6050b1 package mechanical 19/22 table 6. stacked tfbga88 8 10 mm - 8 10 ball array, 0.8 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157
part numbering M36W0R6050T1, m36w0r6050b1 20/22 7 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. table 7. ordering information scheme example: m36 w 0 r 6 0 5 0 t 1 zaq e device type m36 = multiple memory product (multiple flash + ram) flash 1 architecture w = multiple bank, burst mode flash 2 architecture 0 = none present operating voltage r = v ddf = v ddqf = v ddp = 1.7 v to 1.95 v flash 1 density 6 = 64 mbit flash 2 density 0 = none present ram 1 density 5 = 32 mbit ram 0 density 0 = none present parameter blocks location t = top boot block flash b = bottom boot block flash product version 1 = 90 nm flash technology, 70 ns; 0.13 m ram, 70 ns speed package zaq = stacked tfbga88 8 10 mm - 8 10 active ball array, 0.8 mm pitch option e = ecopack? package, standard packing f = ecopack? package, tape & reel packing
M36W0R6050T1, m36w0r6050b1 revision history 21/22 8 revision history table 8. document revision history date revision changes 06-dec-2005 0.1 initial release. 12-jan-2007 1 document status promoted to full datasheet. small text changes.
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